1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming a trench having opposed sidewalls which approach each other as they pass from the upper surface of a semiconductor substrate to the floor of the trench. A gate conductor of a transistor may be formed upon the floor of the trench, and lightly doped drain areas may be formed at the slanted sidewalls of the trench, resulting in a recessed, densely packed transistor.
2. Description of the Relevant Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline silicon ("polysilicon") material over a relatively thin gate oxide arranged above a semiconductor substrate. The polysilicon material and the gate oxide are patterned to form a gate conductor with source and drain regions (i.e., junctions) adjacent to and on opposite sides of the gate conductor. The gate conductor and the source and drain junctions are then implanted with an impurity dopant. If the dopant species employed for forming the source and drain junctions is n-type, then an NMOSFET ("n-channel") transistor device is formed. Conversely, if the dopant species is p-type, then a PMOSFET ("p-channel") transistor device is formed. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single monolithic substrate.
In order to accommodate the high demand for faster, more complex integrated circuits, the threshold voltage of a transistor, V.sub.T, must be reduced. Several factors contribute to V.sub.T, one of which is the effective channel length ("Leff") of the transistor. The initial distance between the source-side junction and the drain-side junction of a transistor is often referred to as the physical channel length. However, after implantation and subsequent diffusion of the junctions, the actual distance between junctions becomes less than the physical channel length and is often referred to as the effective channel length. In ULSI designs, as the physical channel length decreases, so too must the Leff. Decreasing Leff reduces the distance between the depletion regions associated with the source and drain of a transistor. As a result, less gate charge is required to invert the channel of a transistor having a short Leff. Accordingly, reducing the physical channel length, and hence the Leff, can lead to a reduction in the threshold voltage of a transistor. Consequently, the switching speed of the logic gates of an integrated circuit employing transistors with reduced Leff is faster, allowing the integrated circuit to quickly transition between logic states (i.e., operate at high frequencies).
Unfortunately, minimizing the physical channel length of a transistor is somewhat limited by conventional techniques used to define the gate conductor of the transistor. As mentioned earlier, the gate conductor is typically formed from a polysilicon material. A technique known as lithography is used to pattern a photosensitive film (i.e., photoresist) above the polysilicon material. An optical image is transferred to the photoresist by projecting a form of radiation, primarily ultraviolet light, through the transparent portions of a mask plate. The solubility of regions of the photoresist exposed to the radiation is altered by a photochemical reaction. The photoresist is washed with a solvent that preferentially removes resist areas of higher solubility. Those exposed portions of the polysilicon material not protected by photoresist are etched away, defining the opposed sidewall surfaces of a polysilicon gate conductor.
The lateral width (i.e., the distance between opposed sidewall surfaces) of the gate conductor which dictates the physical channel length of a transistor is thus defined by the lateral width of an overlying photoresist layer. The minimum lateral dimension that can be achieved for a patterned photoresist layer is unfortunately limited by, inter alia, the resolution of the optical system (i.e., aligner or printer) used to project the image onto the photoresist. The term "resolution" describes the ability of an optical system to distinguish closely spaced objects. Diffraction effects may undesirably occur as the radiation passes through slit-like transparent regions of the mask plate, affecting the resolution of the optical system. As such, the features patterned upon a masking plate may be incorrectly printed onto the photoresist.
Although shrinking device dimensions advantageously affords increased circuit density and speed, it can also give rise to various problems. Decreasing the Leff of a transistor, for example, generally leads to so-called short-channel effects ("SCE") in which the transistor subthreshold current is increased and the drive current is decreased. Absent a comparable reduction in the depth of the source and drain junctions, the severity of SCE may be profound. The formation of shallow source and drain junctions is, however, rather difficult to accomplish in transistor devices which employ fast-diffusing species as the dopant. Due to their relatively high diffusivity, some dopant species, such as boron, can penetrate deeply into the substrate. Also, advances in technology are required to make available low-energy ion implanters before low implant depths can be realized.
While reducing the junction depth provides protection against SCE, it also undesirably gives rise to increased resistance in the source and drain junctions. As the resistance in the source and drain junctions increases, the saturation drive current and the overall speed of the transistor may drop. Moreover, forming ohmic contacts to relatively shallow junctions has several drawbacks. A contact layer which consumes the underlying source and drain junctions is often used during contact formation. For example, a refractory metal may be deposited across the source and drain junctions and heated to promote a reaction between the metal and the silicon of the underlying substrate. As a result of the reaction, a low resistivity self-aligned silicide (i.e., salicide) may form upon the junctions. The silicide may completely consume relatively shallow junctions, penetrating into the substrate underneath the junctions, a phenomenon known as "junction spiking". Consequently, the junctions may exhibit large current leakage or become electrically shorted. Therefore, precautions must be taken to prevent excessive consumption, and hence junction spiking, of the shallow junctions during contact formation.
It would therefore be desirable to develop a transistor fabrication technique in which the Leff of the transistor is reduced to provide for high frequency operation of an integrated circuit. More specifically, a process is needed in which the channel length is no longer dictated by the resolution of a lithography optical aligner. Furthermore, it would be beneficial for the transistor to be substantially resistant to short channel effects, despite undergoing a reduction in Leff. That is, the transistor design should call for relatively shallow "effective" source and drain regions which have low resistances. While reducing the effective depth of the source and drain regions would be desirable, the actual depth of the source and drain regions must be sufficiently large to avoid problems associated with junction spiking and excessive junction consumption.